This invention relates generally to programmable logic devices (PLDs), and more particularly the invention relates to a PLD having a versatile input cell providing latched, unlatched, and fast inputs.
Programmable logic devices combine the logistical advantages of standard fixed integrated circuits with the architectural flexibility of custom integrated circuits. The PLD allows engineers to electrically program standard off-the-shelf logic elements to meet specific needs of their applications. Thus, proprietary logic functions can be designed and fabricated in-house, eliminating the long engineering lead times, high tool and cost, and other problems associated with a custom application's specific integrated circuit devices, such as gate arrays and standard cells.
The PLD contains programmable AND gate arrays, fixed OR gate arrays, logic array blocks (LABs) including a plurality of macro cells and programmable registers, and programmable input/output (I/O) pins and feedback paths. Heretofore, the I/O pins have been connected through I/O cells which allow the pins to function either clocked or unclocked. The I/O cell then connects the I/O pin through a multiplexer and internal bus to a selected LAB.
The I/O cell introduces delay in the I/O function. Further, the internal bus has inherent resistance and capacitance which further introduces delay, especially in accessing LABs which are far removed from the I/O cell.